1. Field of Invention
The present invention relates to an operation amplification circuit that is capable of low current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to the minimum level, and a constant voltage circuit that uses the operation amplification circuit.
2. Description of Related Art
A conventional operation amplification circuit is shown in FIG. 11. The operation amplification circuit is equipped at least with a bias circuit 1, a differential amplification circuit 2, and an output amplification circuit 3, as shown in FIG. 11.
The bias circuit 1 is a circuit that generates a reference voltage and makes constant a current flowing in a NMOS transistor Q7 of the differential amplification circuit 2 and a current flowing in a NMOS transistor Q9 of the differential amplification circuit 3. For this reason, as shown in FIG. 11, the bias circuit 1 has a PMOS transistor Q1 and an NMOS transistor Q2 serially connected to one another, and the serial circuit is connected between power supply lines 4 and 5.
The differential amplification circuit 2 is a circuit that differentially amplifies a differential signal, and as shown in FIG. 11, is formed from a differential pair of NMOS transistors Q3 and Q4 that is biased by an NMOS transistor Q7 that provides a constant current source. The NMOS transistors Q3 and Q4 are connected to a current mirror circuit that is formed from PMOS transistors Q5 and Q6 as an active load.
The output amplification circuit 3 amplifies and outputs an output signal of the differential amplification circuit 2 by a PMOS transistor Q8 with an NMOS transistor Q9 that is an active load.
In the bias circuit 1 of the conventional operation amplification circuit with the structure described above, the PMOS transistor Q1 can be operated in both of the linear region and the saturation region. Current I that flows in the PMOS transistor Q1 is considered below in both of the cases in which the PMOS transistor Q1 is operated in the linear region and the saturation region.
First, when the PMOS transistor Q1 operates in the linear region, and the power supply voltage VSS is zero (VSS=0), the current I that flows in the PMOS transistor Q1 is provided by Formula (1) as follows:                                                         I              =                              xe2x80x83                            ⁢                                                β                  0                                xc3x97                                  (                                      W                    /                    L                                    )                                ⁢                                  {                                                                                    (                                                                              V                            GS                                                    -                                                      V                            TP                                                                          )                                            xc3x97                                              V                        DS                                                              -                                                                  1                        /                        2                                            xc3x97                                                                        (                                                      V                            DS                                                    )                                                2                                                                              }                                                                                                        =                              xe2x80x83                            ⁢                                                β                  0                                xc3x97                                  (                                      W                    /                    L                                    )                                ⁢                                  {                                                            (                                              VDD                        -                                                  V                          TP                                                                    )                                        xc3x97                                                                                                                                          xe2x80x83                            ⁢                                                                    (                                          VDD                      -                      V1                                        )                                    -                                                            1                      /                      2                                        xc3x97                                                                  (                                                  VDD                          -                          V1                                                )                                            2                                                                      }                                                                        (        1        )            
Also, when the PMOS transistor Q1 operates in the saturation region, the current I that flows in the PMOS transistor Q1 is provided by Formula (1A) as follows:                                                         I              =                              xe2x80x83                            ⁢                                                1                  /                  2                                xc3x97                                  β                  0                                xc3x97                                  (                                      W                    /                    L                                    )                                ⁢                                                      (                                                                  V                        GS                                            -                                              V                        TP                                                              )                                    2                                                                                                        =                              xe2x80x83                            ⁢                                                1                  /                  2                                xc3x97                                  β                  0                                xc3x97                                  (                                      W                    /                    L                                    )                                ⁢                                                      (                                          VDD                      -                                              V                        TP                                                              )                                    2                                                                                        (1A)            
The determination as to which of the regions that the PMOS transistor Q1 operates is made depending on which of the threshold voltages, the threshold voltage VTP of the PMOS transistor Q1 or the threshold voltage VTN of the NMOS transistor Q2, is larger or smaller than the other. When VTP greater than VTN, the PMOS transistor Q1 operates in the saturation region.
In the above Formulas, xcex20 is a constant determined by the process, W is a channel width of the PMOS transistor Q1, L is a channel length of the same, VDD is a power supply voltage, V1 is a drain voltage of the NMOS transistor Q2, and VTP is a threshold voltage of the PMOS transistor Q1.
Also, the PMOS transistor is an enhancement type transistor when it has a positive threshold voltage, and is a depletion type transistor when it has a negative threshold voltage. The description is made throughout the present specification according to this definition.
As indicated in the above Formula (1) and Formula (1A), the current I that flows in the PMOS transistor Q1 depends on the power supply voltage VDD in either the linear region or the saturation region, and increases generally in proportion to the square of the power supply voltage VDD. Also, the current I determines bias currents that flow in the MOS transistors Q2, Q7 and Q9. Accordingly, since the bias current increases in proportion to the square of the power supply voltage VDD, a problem occurs in that the overall power consumption of the operation amplification circuit increases when the power supply voltage VDD varies (increases).
On the other hand, the threshold voltage VTP of the PMOS transistor Q1 is generally determined by Formula (2) as follows.
VTP=xe2x88x92{2xcfx86F+xcfx86Mxe2x88x92xcfx86Sxe2x88x92(QB/C0)xe2x88x92(QSS/C0)}xe2x80x83xe2x80x83(2) 
In Formula (2), xcfx86F is Fermi level of the silicon substrate, xcfx86M is a work function of the gate electrode, xcfx86S is a work function of the silicon substrate, QB is a charge amount in the surface of the silicon, QSS is an interfacial charge amount between the silicon and the oxide film, and C0 is a capacity per unit area of the gate.
Accordingly, since the threshold voltage VTP of the PMOS transistor Q1 is dependent on six parameters, as indicated in Formula (2), variations in the threshold voltage VTP become large. As a result, a problem occurs in that variations in the manufacturing process also cause variations in the current consumption.
Accordingly, it is a first object of the present invention to provide an operation amplification circuit that is capable of reducing the current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to a minimum.
Also, it is a second object of the present invention to provide a constant voltage circuit that uses the above operation amplification circuit, which is capable of reducing the current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to a minimum.
Furthermore, it is a third object of the present invention to provide a reference voltage circuit that can generate a reference voltage that is not dependent on the power supply voltage.
The invention achieves the first object of the invention as discussed below.
Namely, the present invention in accordance with a first aspect includes a differential amplification circuit that receives a differential signal and performs a differential amplification thereof, an output amplification circuit that amplifies an output of the differential amplification circuit, and a bias circuit that determines a bias of the differential amplification circuit and the output amplification circuit. The bias circuit includes a reference voltage circuit that generates a specified reference voltage, and a current mirror circuit based on the reference voltage generated by the reference voltage circuit. The reference voltage circuit includes a first MOS transistor and a second MOS transistor of an identical conduction type that are serially connected to one another. A gate electrode of the first MOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, and a gate electrode of the second MOS transistor is formed from polysilicon including an N-type impurity and is connected to a drain electrode thereof. A voltage corresponding to a difference between threshold voltages of the MOS transistors is generated at a common connection section of the MOS transistors as the reference voltage.
In the operation amplification circuit discussed above, the first MOS transistor can be a depletion type transistor and the second MOS transistor can be an enhancement type transistor.
In the operation amplification circuit discussed above, the first MOS transistors can be serially connected in a plurality of stages.
By the inventions set forth above, the reference voltage circuit can generate a reference voltage that is not dependent on the power supply voltage, whereby a bias current (current consumption) of each of the circuits can be reduced.
Furthermore, in accordance with the invention set forth above, the power supply voltage of the operation amplification circuit (operation amplifier) can be increased compared to the one with one transistor.
The present invention in accordance with another aspect includes a differential amplification circuit that receives a differential signal and performs a differential amplification thereof, an output amplification circuit that amplifies an output of the differential amplification circuit, and a bias circuit that determines a bias of the differential amplification circuit and the output amplification circuit. The bias circuit includes a reference voltage circuit that generates a specified reference voltage; the reference voltage circuit includes a first MOS transistor and a second MOS transistor of an identical conduction type that are serially connected to one another. A gate electrode of the first MOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, and a gate electrode of the second MOS transistor is formed from polysilicon including a P-type impurity and is connected to a source electrode thereof. A voltage corresponding to a difference between threshold voltages of the MOS transistors is generated at a common connection section of the MOS transistors as the reference voltage.
In the operation amplification circuit discussed above, the first MOS transistor can be an enhancement type transistor and the second MOS transistor can be a depletion type transistor.
By the inventions set forth above, the reference voltage circuit can generate a reference voltage that is not dependent on the power supply voltage, whereby the bias current (current consumption) of each of the circuits can be reduced.
In the operation amplification circuit discussed above, the first MOS transistor and the second MOS transistor can be provided with gate electrodes with the same thickness in oxide films thereof, the same carrier mobility and the same dielectric constant.
According to the structure described above, the generated reference voltage of the reference voltage circuit is not dependent on the thickness of the oxide film, the carrier mobility and dielectric constant of the gate electrodes.
In the operation amplification circuit discussed above, the first MOS transistor and the second MOS transistor can have the same channel length and channel width.
According to the structure described above, the generated reference voltage of the reference voltage circuit is not dependent on physical variations in the channel length and channel width of the transistors, which may be caused by variations in the process.
In the operation amplification circuit discussed above, the channel length of each of the first MOS transistor and the second MOS transistor can be shortened and the oxide film of the gate electrode thereof can be thickened by an amount of the channel length shortened.
According to the structure described above, the area of the transistor can be reduced in view of its layout.
In the operation amplification circuit discussed above, the first MOS transistor and the second MOS transistor can have a LOCOS offset structure.
According to the structure described above, the drain dielectric strength of the transistor is enhanced, and therefore the operation voltage of the operation amplification circuit can be increased.
In the operation amplification circuit discussed above, the first MOS transistor and the second MOS transistor can be subject to channel doping under the same condition to lower threshold voltages thereof.
Meanwhile, to achieve the second object of the present invention, another aspect of the invention is provided below.
Namely, the invention includes an operation amplification circuit set forth above; and a trimming circuit that is connected as a load of the output amplification circuit of the operation amplification circuit to optionally divide an output voltage of the output amplification circuit. A generated reference voltage generated by the reference voltage circuit of the operation amplification circuit is input in one of input terminals of the differential amplification circuit of the operation amplification circuit, and a divided voltage of the trimming circuit is input in the other of the input terminals of the differential amplification circuit.
According to the structure described above, the reference voltage circuit can generate a reference voltage that is not dependent on the power supply voltage, such that the bias current (current consumption) can be reduced. Also, since variations in the reference voltage that is generated by the reference voltage circuit are reduced, the amount of trimming can be reduced and therefore the size of the trimming circuit.
Furthermore, to achieve the third object of the present invention, other aspects of the invention are provided below.
Namely, the invention includes a depletion type MOS transistor of a first conduction type is serially connected to an enhancement type MOS transistor of the first conduction type; a first power supply line that supplies a first potential is connected to a gate electrode and a source electrode of the depletion type MOS transistor; and a second power supply line that supplies a second potential lower than the first potential is connected to a gate electrode and a drain electrode of the enhancement type MOS transistor. The gate electrode of the depletion type MOS transistor includes an impurity of the first conduction type. The gate electrode of the enhancement type MOS transistor includes an impurity of the second conduction type. An output terminal is provided at a connection point of the drain electrode of the depletion type MOS transistor and the source electrode of the enhancement type MOS transistor.
Also, in the reference voltage circuit discussed above, a voltage corresponding to a difference between a threshold voltage of the depletion type MOS transistor and a threshold voltage of the enhancement type MOS transistor is generated at the output terminal as a reference voltage.
According to the inventions with the structure described above, a reference voltage that is not dependent on the power supply voltage can be generated.